In prior art synchronizers known to the Applicants, the circuit would revert to the complete initialization and resynchronization process when the circuit determined that there may be an out-of-sync condition. The complete resynchronization process could entail many false starts in selecting all the given logic value or logic zero condition data bits, and checking through enough following frames of data bits to establish whether or not the selected bit position coincides with the actual framing bit.
The present invention, in one embodiment, reverts to an intermediate or confirmation frame sync state whenever three of the most recently received five data bits in the selected framing bit position indicate that the received data bits do not follow the prescribed pattern. When in the intermediate framing bit stage, any further errors in receipt of bits will immediately return the circuit to reinitialize and select a new tentative framing bit position. On the other hand, if enough consecutive framing bits are received having the logic value of the prescribed pattern, the circuit is returned to an established synchronization condition where it will require an additional three out of five bits in error to cause the circuit to determine that there are new signal reception problems.
In other words, the present circuit operates on the principle that if five consecutively received bits in the selected framing bit position follow a predetermined pattern that the correct data bit position has been established. If three out of five later received bits are detected as being incorrect, (after synchronization has been established) it may be assumed that the problem is not in the selection of the wrong framing bit position, but rather in the transmission medium. If any further data bits are received in the data bit position previously selected as the framing bit position, and these bits are received with incorrect values as compared to the predetermined pattern, it may be safely assumed that a new transmission medium needs to be established and resynchronication needs to be commenced from an initial set of values. On the other hand, if the next several framing bit positions provide the correct logic values, it may be correctly assumed that the interference problem causing the incorrect detection of logic values of data bits was a momentary occurrence and that in spite of the interference, synchronization with the transmitter has not actually been lost and thus there is no need to return to the very time consuming process of reestablishing synchronization from "scratch". As will be realized, under the worst possible conditions where there are many logic zero bit positions between framing bits, and where the framing bits alternate in logic value, it could take a large amount of time equal to the time of transmission of many data frames to establish the correct data bit position for the framing bit. Thus, it is very advantageous to temporarily return to the confirmation mode where possible, and reestablish that the correct bit position was selected and is still valid rather than returning to the selection mode to reestablish synchronization.
It is therefore an object of the present invention to provide a synchronization circuit and algorithm which quickly establishes synchronization and can reconfirm synchronization under temporarily adverse conditions.